Semiconductor manufacturers have developed assemblies (also referred to herein as packages), which contain multiple semiconductor dies. For example, systems in a package (SIP) applications can include multiple dies having different configurations, such as a memory configuration, a processing configuration, or an application-specific configuration. The multiple dies can provide increased integration, security and performance in a single package relative to single-die packages.
One aspect of the various multi-die assemblies is that they typically have a relatively large peripheral outline and thickness. For example, conventional SIPs have two or more dies spread out on a common substrate. These assemblies typically have a much larger footprint than conventional single-die semiconductor packages. It would be desirable to develop packages containing multiple dies, and yet efficiently utilizing space. It would also be desirable for such packages to have robust electrical connection between the various dies retained therein.